The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal-oxide semiconductors.
Analog integrated circuits may include active elements such as metal-oxide semiconductors and passive elements such as capacitors and resistors formed on a semiconductor substrate and interconnected by wiring patterns.
U.S. Pat. No. 6,246,084 B1 to Kim describes a method for fabricating a capacitor and resistor over a shallow trench isolation (STI) structure.
U.S. Pat. No. 5,618,749 to Takahashi et al. describes another method for fabricating a capacitor and resistor over a shallow trench isolation (STI) structure.
U.S. Pat. No. 5,434,098 to Chang describes a capacitor process with an interpoly oxide (IPO) layer.
U.S. Pat. No. 5,656,524 to Eklund et al. describes a method of forming a polysilicon resistor.
Accordingly, it is an object of one or more embodiments of the present invention to provide improved methods of simultaneously forming a capacitor(s) and resistor(s) on a field oxide film and a metal-oxide semiconductor(s) on a semiconductor substrate.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having: an exposed oxide structure; a capacitor region within at least a portion of the exposed oxide structure; a first resistor region within at least a portion of the exposed oxide structure; a second resistor region within at least a portion of the exposed oxide structure; and a metal-oxide semiconductor region not within at least a portion of the exposed oxide structure is provided. A first polysilicon layer is formed over the structure and the exposed oxide structure. The first polysilicon layer is doped to form a doped first polysilicon layer. An interpoly oxide film is formed over the doped first polysilicon layer. The interpoly oxide firm is patterned to form: a capacitor interpoly oxide film portion within the capacitor region over the oxide structure; and a second interpoly oxide film portion within the second resistor region over the oxide structure. A second polysilicon layer is formed over the structure. The second polysilicon layer is doped to form a doped second polysilicon layer. The doped second polysilicon layer and the doped first polysilicon layer are patterned to form: within the capacitor region: a lower capacitor doped first polysilicon portion underneath at least a portion of the capacitor interpoly oxide film portion, and an overlying upper capacitor second doped polysilicon portion over at least a portion of the patterned capacitor interpoly oxide film portion; within the first resistor region: a lower first resistor first polysilicon portion and an upper, overlying first resistor second polysilicon portion; within the second resistor region: a lower second resistor first polysilicon portion underneath at least a portion of the second interpoly oxide film portion; and within the metal-oxide semiconductor region: a lower metal-oxide semiconductor first polysilicon portion and an overlying metal-oxide semiconductor second polysilicon portion.